Design of Cost-Efficient Interconnect Processing Units

Name: Design of Cost-Efficient Interconnect Processing Units
Author: France) Grenoble Marcello (STMicroelectronics Coppola

France) Grenoble Marcello (STMicroelectronics Coppola, Greece) Heraklion Miltos D. (ISD SA Grammatikakis, France) Grenoble Cedex Riccardo (STMicroelectronics Locatelli, France) Grenoble Giuseppe (STMicroelectronics Maruccia, Lorenzo (ST Pieralisi

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Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design.

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